1. Field
The present disclosure relates to techniques for storing data in memory modules, and more specifically, interleaving data across memory modules.
2. Related Art
In order to compensate for the relatively low bandwidth provided by certain types of memory, such as DRAM, many computer systems include interleaved memories. In such memories, data is distributed across multiple memory modules, which enables the computer system to subsequently access the data from multiple memory modules in parallel, thereby increasing memory-system throughput. For example, data can be distributed between the memory modules and within the memory modules based on lower-order physical address bits, which results in a fine-grained interleaving of the data between ranks and memory modules.
However, in computer systems that use interleaving, it is often difficult to transition one or more ranks and/or one or more memory modules to an off-line low-power mode without adversely impacting performance. For example, given a page size of 4 or 8 KB, interleaving data based on lower-order physical address bits typically results in portions of each page being distributed to multiple memory modules. Hence, if one of these memory modules is off-lined, a hole is created in the address space within a physical page which can cause the system to crash.
One solution to this problem is to interleave the data across the ranks and/or the memory modules based on higher-order physical address bits. While this interleaving technique can align the physical pages with different memory modules, thereby allowing portions of memory to be off-lined without creating a hole in a physical page, the resulting interleaving is coarse, which reduces parallelism that can be employed while accessing a page. Consequently, there is a tradeoff between performance and power management in such interleaved memory systems.